As a structure for realizing an ultra-fine MISFET with agate length of not longer than 30 nm, a Fin-type channel MISFET (FinFET) and a nanowire-type channel transistor (nanowire transistor) which have strong resistance to a short-channel effect have been expected. In the FinFET, for example, part of a rectangular parallelepiped semiconductor formed on a silicon substrate is taken as a channel region. On both sides of this channel region, a gate electrode is formed so as to sandwich the thin channel region. With the gate electrode structured to surround the channel region, the gate has strong domination to the channel region, and the FinFET realizes strong resistance to the short channel effect.
The nanowire transistor has a structure where the gate electrode is also provided on the top face of the rectangular parallelepiped semiconductor, and a height of the rectangular parallelepiped semiconductor is made smaller. In the nanowire transistor, the top face of the rectangular parallelepiped semiconductor also operates as the channel. A nanowire transistor with a rectangular parallelepiped semiconductor of a relatively large size is also referred to as a Tri-gate transistor.
In manufacturing the FinFET and the nanowire transistor, a SOI substrate is often used rather than a bulk substrate. There are two main reasons for this.
One reason is to be able to use a buried oxide film as a etching stopper on the formation of the rectangular parallelepiped semiconductor layer. The other reason is to be able to reliably suppress a leak current between a source and a drain at OFF-state due to the presence of the buried oxide film as an insulating film under the channel region.
However, the SOI substrate is more expensive than the bulk substrate, thereby inducing an increase in cost of the manufacturing process as a whole. There has thus been considered a nanowire transistor formed on the bulk substrate, with a channel region provided in a polycrystalline semiconductor layer.
It is understood that in the polycrystalline nanowire transistor formed on the bulk substrate, a crystal grain boundary is present in the channel region, thereby causing a problem of inferior characteristics and large variations in characteristics as compared with the nanowire transistor formed on the SOI substrate.